1. Field of the Invention
The present invention relates to clock control circuit and method for controlling a clock supplied to a flip flop circuit incorporated in a logic circuit, and in particular, to a clock control circuit and method for supplying a test clock to a flip flop circuit instead of a normal clock.
This application is based on Japanese Patent Application No. 11-291662, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In recent years, as the operating speeds of LSIs have increased, means for early detection of a delay failures have becomes important. In general, a high speed test using a high speed tester is executed to detect delay failures. High speed testers, however, are expensive, and increase the costs of the test. As a technique which enables testing using an inexpensive tester, a delay test method using the scan path test function has received attentions.
The delay test using the scan path test function cannot effectively set the path for the test target, e.g., when the target is a degeneracy failure, and cannot produce a test pattern with a high failure detection rate.
To solve the problem, a conventional technique disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 3-61872 (Patent No. 2619957) is known. As shown in FIG, 13, in the conventional technique, a plurality of latches 1, included in a logic circuit which is the test target, are classified into a plurality of groups, and OS latches 2 for controlling the supply/stop of the clock are provided for the respective latch groups.
According to the conventional technique, for example, when testing the signal transfer time of the path from the source latch 1-1 to the target latch 1-2, the OS latches (1) and (3), provided for the group to which the source latch 1-1 and the target latch 1-2 belong, are set to the xe2x80x9ceffective valuexe2x80x9d, and the other OS latches are set to xe2x80x9cinvalid valuexe2x80x9d. Thus, the clock is supplied only to the latches in the group to which the source latch 1-1 and the target latch 1-2 belong, and is not supplied to the latches in the other groups.
After the values are thus set in the OS latches, when the clock CLK1 is applied to the source latch 1-1, test data is input to the source latch 1-1 and is output to the path. When applying the clock CLK2 after the data travels through the path and reaches the target latch 1-2, the data is appropriately received by the target latch 1-2. When applying the clock CLK2 before the arrival of the data, the data is not received correctly. That is, the time of the arrival of the data at the target latch 1-2 can be known, based on the point in time of the clock CLK2 when the data to be received by the target latch 1-2 is changed. The signal transfer time can be computed from the difference in time between the clocks CLK1 and CLK2.
According to the technique, even when on the path between the source latch 1-1 and the target latch 1-2 there is a gate circuit 1-30 controlled by a value set in a latch 1-3 in the group containing the OS latch (2), the value in the latch 1-3 is not changed as long as the effective value is set in the OS latch (2). Thus, the destruction of the signal transfer path due to the delay test can be prevented.
In the above-mentioned conventional technique, however, the clock must be externally input into the latches to know the point in time of the clock in the latches. Therefore, the test target is disadvantageously limited to paths between the latches which can receive the external clock. For example, a path between flip flop circuits which are controlled by a clock generated inside an LSI cannot be tested, and thus the flexibility of the logic circuit test is degraded.
It is therefore an object of the present invention to provide a clock control circuit which can supply an appropriate test clock to flip flop circuits such as a latch incorporated in a logic circuit, improving the flexibility of the logic circuit test.
The clock control circuit of the present invention for controlling a clock supplied to a plurality of flip flops (21 to 23 and 31 to 33) incorporated in a logic circuit (paths 101 to 103), comprises a plurality of clock suppliers (11 to 13), coupled to the respective flip flops. Each of the clock suppliers performs the logical operation with a normal clock (CLK1 to CLK3) and a test clock (TCLK1 to TCLK3) to allow one of the normal clock and the test clock to pass, using the other clock as a control signal, and supplies the passing clock to the flip flops.
According to the circuit, the clock supplier functions as a logic gate circuit, such as an OR circuit, or an AND circuit, performs the logical operation with the test clock and the normal clock, and allows one of the normal clock and the test clock to pass, using the other clock as a control signal. For example, when the clock supplier functions as an OR circuit, the normal clock input to the clock supplier is the control signal, and is fixed to 0. Then, the output from the clock supplier is the same value as the test clock so that the clock supplier allows the test clock to pass. Conversely, when the test clock is used as the control signal and is fixed to 0, the clock supplier outputs the same value as the normal clock, and allows the normal clock to pass. Therefore, the normal clock or the test clock, which has passed through the clock supplier, is supplied to the flip flops in the logic circuit.
The clock suppliers allow one of the test clock and the normal clock to pass, using the other clock as the control signal, and supply the passing clock to the flip flops. In other words, the clock suppliers select one of the normal clock and the test clock, and supply the selected clock to the corresponding flip flops. Thus, the test clock can be optionally supplied to the flip flops incorporated in the logic circuit. Thus, the test clock can be optionally supplied to the flip flops incorporated in the logic circuit, and the flexibility of the test for the logic circuit is improved.
Further, the clock control circuit of the present invention, further comprises a clock distributor (40) for distributing the test clock (TCLK1 to TCLK3) to the clock suppliers, depending on data (RDATA) for selecting flip flop circuits.
According to the structure, the test clock is distributed to the clock supplier, depending on the data indicating the selected/unselected flip flops. The clock supplier, which receives the test clock, supplies the test clock to the flip flops. That is, the test clock is supplied only to the flip flops which are selected by the data, and the selected flip flops operate synchronously with the test clock. At that time, the flip flops which are not selected by the data do not operate, and fix their output. Therefore, by setting the data, the test clock is optionally supplied to a plurality of the flip flops, such as latches in the logic circuit, and the clock for those flip flops can be optionally controlled, This prevents the flop flops, which are not the test targets, from operating, and prevents the transmission line of the test target path from being destroyed.
Further, the clock distributor of the present invention comprises: a register (410) for storing the data; and a gate (420) for selectively outputting the test clock to the clock suppliers, depending on the data stored in the register.
According to the structure, the register stores the data indicating the selected/unselected flip flops, and the gate outputs the test clock to the clock suppliers, depending on the data stored in the register. For example, when the data stored in the register does not select any flip flop, the test clock is not output. When the data stored in the register selects the flip flops, the test clock is output. That is, the gate outputs the test clock selectively to the clock supplier, depending on the data stored in the register.
Further, the clock distributor of the present invention further comprises a selector (500) for selecting one of a plurality of prepared signals (DTCLK, or STCLK), and outputting the selected signal as the test clock to the gate.
According to the structure, by selecting the various prepared signal with the selector, the contents of the test clock are changed. Therefore, the test clock, which each of the clock suppliers is to supply to the flip flop, can be changed.
Further, in the present invention, a plurality of prepared signals include at least a clock signal (STCLK) for a degeneracy failure test, and a clock signal (DTCLK) for a delay test.
According to the structure, the test clock, which each of the clock suppliers is to supply to the flip flop, is selected from the clock signal for the degeneracy failure test and the clock signal for the delay test. Thus, as the tests for the logic circuits, both the degeneracy test and the delay test can be executed.
When the data does not select any flip flop, the gate may output the logic value which maintains the outputs from the flip flops. Thus, the outputs from the flip flops which are not selected are not changed, and only the selected flip flops operate.
Further, the clock control method of the present invention for controlling a clock supplied to a plurality of flip flops (21 to 23 and 31 to 33) incorporated in a logic circuit (paths 101 to 103), comprises the step (S10, or S11) of performing the logical operation with a normal clock (CLK1 to CLK3) and a test clock (TCLK1 to TCLK3) to allow one of the normal clock and the test clock to pass, using the other clock as a control signal, and supplying the passing clock to the flip flops.
Further, the clock control method of the present invention for controlling a clock supplied to a plurality of flip flops (21 to 23 and 31 to 33) incorporated in a logic circuit (paths 101 to 103), comprises: a first step (S10) of outputting a test clock (TCLK1 to TCLK3), depending on data (RDATA) for selecting flip flop circuits; and a second step (S11) of performing the logical operation with a normal clock (CLK1 to CLK3) and the test clock to allow one of the normal clock and the test clock to pass, using the other clock as a control signal, and supplying the passing clock to the flip flops.
The first step includes performing the logical operation with the data and the test clock to selectively output the test clock, depending on the data (the function of the clock distributing circuit 40).
The first step includes selecting one of a plurality of prepared signals (DTCLK and STCLK), and outputting the selected signal as the test clock (the function of the selecting circuit 500).